Truth Table
Waveform Diagram
Karnaugh Map
Algebraic Proof
Quine-McCluskey
Gate Level Verilog
Dataflow Verilog
Initializing Logic Engine...
Type any Boolean expression, minterm list, or K-Map size to instantly get a simplified SOP/POS result, a step-by-step algebraic and Quine-McCluskey proof, an auto-generated Karnaugh map, a full truth table, an interactive simulated circuit diagram, and exportable gate-level or dataflow Verilog code — all free, offline-capable, and running entirely in your browser.